1. Field of the Invention
The present invention relates to a clock generating circuit, and more particularly to a clock synchronizing circuit for generating an internal clock signal synchronized in phase with a reference clock signal.
2. Description of the Background Art
FIG. 18 shows an example of a configuration of a conventional clock generator. By way of example, the figure shows a configuration of a phase synchronizing circuit (phase locked loop circuit (PLL circuit)) including a voltage controlled oscillating circuit of a ring oscillator type.
As shown in FIG. 18, the clock generator includes: a phase comparison circuit PH for comparing a phase of a reference clock signal having a predetermined cycle C and a phase of a recovered clock signal CO and producing a signal according to the phase difference; a charge pump/low pass filter CPLP including a charge pump performing a charge pumping operation according to the phase difference detection signal produced from the phase comparison circuit PH to generate a control voltage and a low pass filter for removing a high frequency component of the control voltage produced from the charge pump; a bias controlling circuit BK for generating bias voltages V1 and V2 in accordance with the control voltage from the charge pump/low pass filter; a voltage controlled oscillation circuit O having an oscillation frequency controlled in accordance with the bias voltages V1 and V2 from the bias control circuit BK. voltages produced by the charge pump. Bias control circuit BK generates bias voltages V1 and V2 according to the control voltages produced by charge pump/low pass filter CPLP. Voltage controlled oscillation circuit O controls oscillation frequencies according to bias voltages V1 and V2 produced by Bias control circuit BK.
Phase comparison circuit PH compares the phases of reference clock signal C and recovered clock signal CO, and produces an up-signal for increasing a frequency of the recovered clock signal CO or a down-signal for decreasing the frequency of the recovered clock signal CO in accordance with the phase difference.
In charge pump/low pass filter CPLP, the charge pump performs charge/discharge operation in response to the up- or down-signal received from phase comparison circuit PH, and the low pass filter performs the integration of the charged potential due to the charge/discharge current generated by the charge pump, for generating the control voltage. The low pass filter is normally called a loop filter.
Bias control circuit BK receives the control voltage from charge pump/low pass filter CPLP, and generates bias voltages V1 and V2 for adjusting the oscillation frequency of oscillation circuit O.
Oscillation circuit O includes an odd-number of stages of delay cells D1 to Dn coupled in a ring form. In delay cells D1 to Dn, a cell signal of a preceding stage is sequentially transferred to a delay cell of a subsequent delay cell, and the recovered clock signal CO generated from the final-stage delay cell Dn is fed-back to the delay cell D1 of the initial stage. Delay cells D1 to Dn each have an identical configuration, and therefore, in FIG. 18, reference characters are attached to components of only the final-stage delay cell Dn.
Delay cell Dn includes: a current source transistor MC1 having a driving current thereof controlled in accordance with the bias voltage V1; an insulated gate field effect transistor (referred to as an MOS transistor) M5 of a p channel type connected between the current source transistor MC1 and an output node, for receiving an output signal of the delay cell of a preceding stage at a gate thereof; an n-channel MOS transistor M6; and a current source transistor MC2 connected between MOS transistor M6 and the ground node, for receiving the bias voltage V2 at a gate thereof signal of the previous-stage delay cell. Current source transistor MC2 is coupled between MOS transistor M6 and a ground node, and the gate of transistor MC2 receives bias voltage V2.
Current source transistor MC1 is formed of a p-MOS transistor. Current source transistor MC2 is formed of an n-MOS transistor. Each of delay cells D1 to Dn is formed of a CMOS inverter having the driving current set current source transistors MC1 and MC2.
When the level of the bias voltage V1 rises, and the level of the bias voltage V2 decreases, the conductance of each of the current source transistors MC1 and MC2 are reduced, and the amount of the drive current thereof is reduced accordingly. Responsively, the operation speeds of delay cells D1 to Dn are reduced. Accordingly, the oscillation cycle of oscillation circuit O is increased, and the oscillation frequency thereof is reduced.
When the level of bias voltage V1 lowers and the level of the bias voltage V2 increases, the conductances of current source transistors MC1 and MC2 increase, and the amount of the drive current thereof increases. Responsively, the operation currents of the respective delay cells D1 to Dn increase, to increase the operation speeds thereof, and the oscillation cycle of oscillation circuit O decreased to increase the frequency of recovered clock signal CO.
The oscillation cycle of oscillation circuit O is controlled through bias voltages V1 and V2 in accordance with the phase difference between reference clock signal C and recovered clock signal CO, to synchronize in phase the reference clock signal C with the recovered clock signal CO. Thus, the recovered clock signal CO that tracks in frequency the reference clock signal C is generated.
FIG. 19 shows an example of the configuration of bias control circuit BK shown in FIG. 18. Referring to FIG. 19, bias control circuit BK includes: an n-MOS transistor M1 connected between a node AN and the ground node, and receiving the control voltage VC at a gate thereof; a p-channel MOS transistor M2 connected between a power supply node and node AN, and having a gate connected to node AN; a p-MOS transistor M3 connected between the power supply node and a node BN, and having a gate connected to node AN; and an n-MOS transistor M4 connected between node BN and the ground node, and having a gate connected to node BN.
MOS transistors M2 and M3 form a current mirror circuit, in which a mirror current of the current flowing through MOS transistor M2 flows through MOS transistor M3. That is, when MOS transistors M2 and M3 are the same in size (ratio of the channel width to the channel length) with each other, the currents of the same magnitude flow through MOS transistors M2 and M3.
Control voltage VC is supplied from charge pump/low pass filter CPLP shown in FIG. 18.
When the level of control voltage VC rises, the conductance of MOS transistor M1 increases, and the current flowing through MOS transistor M1 increases. The current is supplied to MOS transistor M1 from MOS transistor M2, the amount of the current flowing via MOS transistor M2 is thereby increased, and the current flowing via MOS transistor M3 is increased accordingly. Since MOS transistor M2 has the gate and drain thereof coupled together, and has the supply current thereof increased, the voltage level of node AN lowers. On the other hand, MOS transistor M4 has the gate and drain thereof coupled to node BN, and has to discharge the current supplied from MOS transistor M3. Accordingly, the voltage level of node BN rises.
Specifically, when control voltage VC increases, the level of bias voltage V1 lowers, while the level of bias voltage V2 rises, conversely. These bias voltages V1 and V2 are supplied to the gates of current source transistors MC1 and MC2, respectively. Thus, in oscillation circuit O, the operation currents of delay cells D1 to Dn increase, and the operation speeds thereof increase accordingly. Consequently, the oscillation cycle of oscillation circuit O is decreased, and the frequency of recovered clock signal CO is increased.
When the level of control voltage VC lowers, the conductance of MOS transistor M1 decreases, and the drive current thereof decreases. Accordingly, the amount of the supply current of MOS transistor M2 decreases, the gate to source voltage of MOS transistor M2 decreases, and the voltage level of node AN rises. In addition, through the current mirror operation, the amount of the current supplied via MOS transistor M3 is reduced to decrease the gate to source voltage of MOS transistor M4, resulting in a decreased voltage level of node BN. Accordingly, the level of bias voltage V1 increases and the level of bias voltage V2 decreases. Accordingly, in oscillation circuit O shown in FIG. 18, the operation currents of delay cells D1 to Dn are reduced, and the operation speeds thereof are reduced. Concurrently, delay times of delay cells D1 to Dn are increased to prolonged. For these reasons, the oscillation cycle of oscillation circuit O is decrease the frequency of recovered clock signal CO.
In phase comparison circuit PH, the up-signal/down-signal is generated in accordance with the lead/lag in the phase of recovered clock signal CO relative to reference clock signal C. In response to the up-signal/down-signal, control voltage VC is generated in charge pump/low pass filter CPLP. Thereby, the frequency and the phase of recovered clock signal CO are adjusted, and recovered clock signal CO phase-synchronized with reference clock signal C is generated.
FIG. 20 shows the relationship between control voltage VC and the frequency of recovered clock signal. As shown in FIG. 20, in proportion to the increase in control voltage VC, an oscillation frequency FB of the oscillator increases. Hereinbelow, a range of frequency in which the clock generator stably oscillates is referred to as a xe2x80x9cfrequency rangexe2x80x9d, and a range of the control voltage at which voltage controlled oscillation circuit O operates is referred to as a xe2x80x9cvoltage rangexe2x80x9d.
For a stable operation of a phase synchronization loop, it is desirable for the center value of the frequency range, central frequency, to coincide with a central value of the voltage range. Thereby, the oscillation frequency of voltage controlled oscillation circuit O can be increased or reduced by increasing or reducing control voltage VC with respect to the central frequency. This enables a phase-locked recovered clock signal CO to be stably generated at a high speed even when the frequency of reference clock signal C deviates from the central frequency. Generally, the circuit design is made such that central frequency fcm coincides with central value VCm of the voltage range. However, because of the occurrence of, for example, variations in transistor parameters in a manufacturing step, deviation frequently occurs between the designed value and the actual value after manufacture, and such deviation needs to be corrected.
FIG. 21 shows variations in the characteristics of voltage controlled oscillation circuit O shown in FIG. 18. In voltage controlled oscillation circuit O, as a design value, a voltage VCm is set as the middle value of control voltage for the central frequency. In this case, the characteristics of a typical voltage controlled oscillator (VCO) are obtained, in which the frequency linearly varies substantially in the frequency range according to control voltage VC.
When the operation speed of voltage controlled oscillation circuit O is increased because of, for example, variation in a transistor parameter in a manufacturing step, the designed central frequency is given by a control voltage VCa. That is, when the operation speed of voltage controlled oscillation circuit O is increased because of a variation in transistor parameter in a manufacturing step, VCO characteristics thereof deviate toward the left side in FIG. 21. Accordingly, the position of the central frequency shifts.
In contrast, when the operation speed of voltage controlled oscillation circuit O is reduced because of a variation in transistor parameter in a manufacturing step, a control voltage VCb needs to be supplied to control the frequency to be phase-synchronous to the designed central frequency. In this case, VCO characteristics deviate toward the right side in FIG. 21.
Specifically, with the same reference clock signal C applied, the lock voltage (control voltage) for phase synchronization varies because of variations in manufacturing parameters. Now, it is assumed that symbol KOm represents the sensitivity of the voltage controlled oscillator that has VCO characteristics coincident with design values (typical VCO characteristics). Sensitivity KOm is here defined to indicate the variation of the oscillation frequency with respect the variation of the control voltage VC. In this case, sensitivity KOa of a voltage controlled oscillator having fast VCO characteristics is higher than typical sensitivity KOm, while sensitivity KOb of a voltage controlled oscillator having slow VCO characteristics is lower than typical sensitivity KOm. In these voltage controlled oscillators having the VCO characteristics deviating from typical VCO characteristics, the variation of the oscillation frequency to the variation of the control voltage is different from the designed value. Consequently, a phase-synchronized, recovered clock signal can not be stably generated for the frequency deviating from the central frequency.
In particular, in a xe2x80x9chigh-sensitivexe2x80x9d voltage controlled oscillator in which the central frequency is substantially fixed, and the frequency variation is small, the deviation needs to be corrected to cause oscillation to be made at the central frequency. In addition to the configuration that generates a recovered clock signal which is phase-synchronous with a single speed reference clock signal, there is a field requiring to reproduce multi speed clock signals. For example, in a communication field, since the data transmission rate is various, multi speed reference clock signals are transmitted in accordance with the applications, and it is required to recover clock signals corresponding to the received reference clock signal. In such a field, such a problem arises that if the VCO characteristics are deviated, recovered clock signals that are phase synchronous with or phase locked to the multi speed clock signals can not be generated accurately.
An object of the present invention is to provide a clock generator capable of optimally correcting a deviation in frequency characteristics caused in a manufacturing step.
Another object of the present invention is to provide a clock generator capable of controlling a voltage controlled oscillator to stably oscillate at a central frequency.
Still another object of the present invention is to provide a clock generator capable of generating recovered clock signals that are stably phase synchronous with a reference signal regardless of deviation in a manufacturing step.
A clock generator of the present invention includes: a first oscillator; a power supply controller for adjusting a potential of a power supply line for a first oscillator according to a phase difference between an oscillation signal of the first oscillator and a first reference clock signal; a second oscillator receiving the potential of the power supply line as an operation power supply voltage, for performing an oscillation operation; and a bias control circuit for adjusting an operation speed of the second oscillator according to a phase difference between an output signal of the second oscillator and a second reference clock signal.
According to the present invention, the potential of the power supply line of the first oscillator is adjusted in accordance with the phase difference between the oscillation signal of the first oscillator and first reference clock signal. The adjusted potential of the power supply line is supplied to the second oscillator as the operation power supply potential for the second oscillator. The operation speed of the second oscillator is adjusted according to the phase difference between the output signal of the second oscillator and the second reference clock signal. Thus, even when a variation occurs in manufacturing parameter, the frequency characteristics of the first oscillator are so adjusted as to compensate for the variation in the manufacturing parameter, and accordingly the frequency characteristics of the second oscillator can be adjusted. Therefore, regardless of the variation in the manufacturing parameter, the clock generator capable of stably operating with designed frequency characteristics can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.